| 专利名称 | FDSOI semiconductor structure and method for manufacturing the same | 申请号 | US201214397586 | 专利类型 | US | 公开（公告）号 | US9548317(B2) | 公开（授权）日 | 2017.01.17 | 申请（专利权）人 | 中国科学院微电子研究所 | 发明（设计）人 | Yin Haizhou;Zhu Huilong;Luo Zhijiong | 主分类号 | H01L21/84 | IPC主分类号 | H01L21/84;H01L27/12;H01L29/66;H01L29/786;H01L21/02;H01L21/266;H01L21/306;H01L21/308;H01L21/768;H01L29/78;H01L21/74;H01L21/265;H01L29/165 | 专利有效期 | FDSOI semiconductor structure and method for manufacturing the same 至FDSOI semiconductor structure and method for manufacturing the same | 法律状态 | 说明书摘要 | The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly. |
1、源头对接，价格透明
2、平台验证，实名审核
3、合同监控，代办手续
4、专员跟进，交易保障