| 专利名称 | Semiconductor device with back gate isolation regions and method for manufacturing the same | 申请号 | US201113504643 | 专利类型 | US | 公开（公告）号 | US9214400(B2) | 公开（授权）日 | 2015.12.15 | 申请（专利权）人 | 中国科学院微电子研究所 | 发明（设计）人 | Zhu Huilong;Liang Qingqing;Luo Zhijiong;Yin Haizhou | 主分类号 | H01L27/12 | IPC主分类号 | H01L27/12;H01L21/84 | 专利有效期 | Semiconductor device with back gate isolation regions and method for manufacturing the same 至Semiconductor device with back gate isolation regions and method for manufacturing the same | 法律状态 | 说明书摘要 | The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs. In addition to back gate isolation implemented by the shallow trench isolation between the adjacent MOSFETs, the adjacent MOSFETs are also isolated by means of PNPN junctions or NPNP junctions formed in the back gates and the back gate isolation regions. As a result, the semiconductor device has a better isolation effect, and thus the possibility of accidental breakdown of the semiconductor device is substantially reduced. |
1、源头对接，价格透明
2、平台验证，实名审核
3、合同监控，代办手续
4、专员跟进，交易保障