| 专利名称 | Method for manufacturing semiconductor device | 申请号 | US201214355919 | 专利类型 | US | 公开（公告）号 | US9136181(B2) | 公开（授权）日 | 2015.09.15 | 申请（专利权）人 | 中国科学院微电子研究所 | 发明（设计）人 | Xu Qiuxia;Zhu Huilong;Xu Gaobo;Zhou Huajie;Chen Dapeng | 主分类号 | H01L21/8238 | IPC主分类号 | H01L21/8238;H01L29/78;H01L29/49;H01L29/51;H01L21/02;H01L21/266;H01L21/28;H01L21/3105;H01L21/321;H01L21/3213;H01L21/324;H01L29/167;H01L29/423;H01L29/66 | 专利有效期 | Method for manufacturing semiconductor device 至Method for manufacturing semiconductor device | 法律状态 | 说明书摘要 | A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer. |
1、源头对接，价格透明
2、平台验证，实名审核
3、合同监控，代办手续
4、专员跟进，交易保障