| 专利名称 | Method for integration of dual metal gates and dual high-K dielectrics in CMOS devices | 申请号 | US201113129743 | 专利类型 | US | 公开（公告）号 | US8748250(B2) | 公开（授权）日 | 2014.06.10 | 申请（专利权）人 | 中国科学院微电子研究所 | 发明（设计）人 | Xu Qiuxia;Xu Gaobo | 主分类号 | H01L21/8238 | IPC主分类号 | H01L21/8238 | 专利有效期 | Method for integration of dual metal gates and dual high-K dielectrics in CMOS devices 至Method for integration of dual metal gates and dual high-K dielectrics in CMOS devices | 法律状态 | 说明书摘要 | The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy and a large angle for source/drain extensions; forming a second spacer, and performing ion implantation for source/drain regions; performing a thermal annealing so as to adjust of the metal gate work functions for the NMOS and PMOS devices, respectively, in the course when the dopants in the source/drain regions are activated. |
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