Semiconductor device with a common back gate isolation region and method for manufacturing the same

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专利名称 Semiconductor device with a common back gate isolation region and method for manufacturing the same 申请号 US201113510807 专利类型 US 公开(公告)号 US9054221(B2) 公开(授权)日 2015.06.09 申请(专利权)人 中国科学院微电子研究所 发明(设计)人 Zhu Huilong;Liang Qingqing;Luo Zhijiong;Yin Haizhou 主分类号 H01L27/088 IPC主分类号 H01L27/088;H01L21/336;H01L21/84;H01L27/12 专利有效期 Semiconductor device with a common back gate isolation region and method for manufacturing the same 至Semiconductor device with a common back gate isolation region and method for manufacturing the same 法律状态 说明书摘要 The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.

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