Method for manufacturing semiconductor structure

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专利名称 Method for manufacturing semiconductor structure 申请号 US201113133120 专利类型 US 公开(公告)号 US9202913(B2) 公开(授权)日 2015.12.01 申请(专利权)人 中国科学院微电子研究所 发明(设计)人 Zhu Huilong 主分类号 H01L21/8238 IPC主分类号 H01L21/8238;H01L29/78;H01L29/66 专利有效期 Method for manufacturing semiconductor structure 至Method for manufacturing semiconductor structure 法律状态 说明书摘要 The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.

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