| 专利名称 | Multi-phase clock signal generation circuits | 申请号 | US201113574229 | 专利类型 | US | 公开（公告）号 | US8963605(B2) | 公开（授权）日 | 2015.02.24 | 申请（专利权）人 | 中国科学院微电子研究所 | 发明（设计）人 | Chen Weiwei;Chen Lan;Long Shuang | 主分类号 | H03K3/00 | IPC主分类号 | H03K3/00;G06F1/04 | 专利有效期 | Multi-phase clock signal generation circuits 至Multi-phase clock signal generation circuits | 法律状态 | 说明书摘要 | Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump. |
1、源头对接，价格透明
2、平台验证，实名审核
3、合同监控，代办手续
4、专员跟进，交易保障